Kreeger Research hdl:verilog
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2026-05-25T12:09:45+0000Kreeger Research
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http://kreegerresearch.com/wiki/lib/tpl/monobook/images/favicon.icotext/html2010-01-14T19:42:49+0000Anonymous (anonymous@undisclosed.example.com)hdl:verilog:blockingassignments
http://kreegerresearch.com/wiki/doku.php?id=hdl:verilog:blockingassignments&rev=1263498169&do=diff
Blocking Assignment
The definition of a blocking statement is the execution occurs sequentially from left to right, top to bottom. Verilog has a sequential block of code (between begin and end) each assignment occurs one after another.
Example
module BLOCKING;
integer A;
initial $dumpvars(0,BLOCKING);
initial
begin
A = 1; // Do this first, Set A to 1
A = 2; // Do this second, Set A to 2
A = #10 3; // Set A to 3 after 10 timesteps
A = #12 4; // Set A to 4 aft…text/html2010-01-14T19:42:49+0000Anonymous (anonymous@undisclosed.example.com)hdl:verilog:icarusverilogsetupmac
http://kreegerresearch.com/wiki/doku.php?id=hdl:verilog:icarusverilogsetupmac&rev=1263498169&do=diff
Icarus Verilog and GTKWave on a Mac
Installation:
The easiest way to install all the software is to use a package manager. I use MacPorts which makes it very easy to install all the dependent packages. Typically MacPorts is installed in a separate directory than the Mac