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- | ====== Partners ====== | ||
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- | * Impulse Accelerated Technologies, INC. | ||
- | * [[http://Impulsec.com/|Impulses WebSite]] | ||
- | * | ||
- | ====== Math.h ImpulseC comparison ====== | ||
- | |||
- | Here are the main advantages: | ||
- | - Reduced code reduces chances of user coding errors. | ||
- | - Impulse takes care of piplinging and synchronization issues. | ||
- | - Fast iterative algorithm development. | ||
- | |||
- | <code c> | ||
- | #include <math.h> | ||
- | |||
- | void main(void) { | ||
- | float x,y; | ||
- | x = 2.9; | ||
- | y = logf(x); | ||
- | printf("result=%f\n",y); | ||
- | |||
- | } | ||
- | </code> | ||
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- | Note: the following code is for illustration prepossess only and does not everything that is necessary for synchronization for real time pipelined systems. | ||
- | <code vhdl> | ||
- | library ieee; | ||
- | use ieee.std_logic_1164.all; | ||
- | |||
- | library impulse; | ||
- | use impulse.components.all; | ||
- | | ||
- | use impulse.xilinx_float_math_fast.all; | ||
- | | ||
- | use impulse.xilinx_float_fast.all; | ||
- | |||
- | entity dut is | ||
- | port (signal reset : in std_ulogic; | ||
- | signal sclk : in std_ulogic; | ||
- | signal clk : in std_ulogic; | ||
- | signal y_out_rdy : in std_ulogic; | ||
- | signal y_out_data : out std_ulogic_vector (31 downto 0)); | ||
- | end dut; | ||
- | |||
- | architecture rtl of dut is | ||
- | signal val_x : std_ulogic_vector (31 downto 0); | ||
- | signal val_y : std_ulogic_vector (31 downto 0); | ||
- | begin | ||
- | |||
- | val_x <= X"0x4039999a" -- represents a float value of 2.9 | ||
- | | ||
- | logf_fast_0: logf_fast | ||
- | port map ( | ||
- | clk => clk, | ||
- | a => val_x, | ||
- | go => '1', | ||
- | result => y_out_rdy, | ||
- | pipeEn => y_out_rdy); | ||
- | | ||
- | end rtl; | ||
- | </code> | ||
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