====== Blocking Assignment ======
The definition of a blocking statement is the execution occurs sequentially from left to right, top to bottom. Verilog has a sequential block of code (between begin and end) each assignment occurs one after another.
===== Example =====
<code verilog>
module BLOCKING;
  integer A;
  initial $dumpvars(0,BLOCKING);
  initial
    begin
      A = 1; // Do this first, Set A to 1
      A = 2; // Do this second, Set A to 2
      A = #10 3; // Set A to 3 after 10 timesteps
      A = #12 4; // Set A to 4 after 12 timesteps
      A = #20 5; // Set A to 5 after 20 timesteps
      #10 $finish; // Exit the simulation
    end

  always @ (A)
    begin
      $write("%d: A = %dn",$time,A);
    end
endmodule
</code>

====== Non-Blocking Assignment ======
===== Example =====
<code verilog>
module NONBLOCKING;
  integer A;
  initial $dumpvars(0,NONBLOCKING);
  initial
    begin
      A = 1;
      A = 2;
      A <= #10 3;
      A <= #12 4;
      A <= #20 5;
    end

  always @ (A)
    begin
      $write("%d: A = %dn",$time,A);
    end
endmodule
</code>